/*--------------------------------------------------------------------------
N76E003.H

Header file for Nuvoton N76E003
--------------------------------------------------------------------------*/

#ifndef __N76E885_H__
#define __N76E885_H__

sfr P0          = 0x80;
sfr SP          = 0x81;
sfr DPL         = 0x82;
sfr DPH         = 0x83;
sfr RWK         = 0x86;
sfr PCON        = 0x87;

sfr TCON        = 0x88;
sfr TMOD        = 0x89;
sfr TL0         = 0x8A;
sfr TL1         = 0x8B;
sfr TH0         = 0x8C;
sfr TH1         = 0x8D;
sfr CKCON       = 0x8E;
sfr WKCON       = 0x8F;

sfr P1          = 0x90;
sfr SFRS        = 0x91; //TA Protection
sfr CAPCON0     = 0x92;
sfr CAPCON1     = 0x93;
sfr CAPCON2     = 0x94;
sfr CKDIV       = 0x95;
sfr CKSWT       = 0x96; //TA Protection
sfr CKEN        = 0x97; //TA Protection

sfr SCON        = 0x98;
sfr SBUF        = 0x99;
sfr SBUF_1      = 0x9A;
sfr EIE         = 0x9B;
sfr EIE1        = 0x9C;
sfr CHPCON      = 0x9F; //TA Protection

sfr P2          = 0xA0;
sfr AUXR1       = 0xA2;
sfr BODCON0     = 0xA3; //TA Protection
sfr IAPTRG      = 0xA4; //TA Protection
sfr IAPUEN      = 0xA5;	//TA Protection
sfr IAPAL       = 0xA6;
sfr IAPAH       = 0xA7;

sfr IE          = 0xA8;
sfr SADDR       = 0xA9;
sfr WDCON       = 0xAA; //TA Protection
sfr BODCON1     = 0xAB; //TA Protection
sfr P3M1        = 0xAC;
sfr P3S         = 0xAC; //Page1
sfr P3M2        = 0xAD;
sfr P3SR        = 0xAD; //Page1
sfr IAPFD       = 0xAE;
sfr IAPCN       = 0xAF;

sfr P3          = 0xB0;
sfr P0M1        = 0xB1;
sfr P0S         = 0xB1; //Page1
sfr P0M2        = 0xB2;
sfr P0SR        = 0xB2; //Page1
sfr P1M1        = 0xB3;
sfr P1S         = 0xB3; //Page1
sfr P1M2        = 0xB4;
sfr P1SR        = 0xB4; //Page1
sfr P2S         = 0xB5; 
sfr IPH         = 0xB7;
sfr PWMINTC		= 0xB7;	//Page1

sfr IP          = 0xB8;
sfr SADEN       = 0xB9;
sfr SADEN_1     = 0xBA;
sfr SADDR_1     = 0xBB;
sfr I2DAT       = 0xBC;
sfr I2STAT      = 0xBD;
sfr I2CLK       = 0xBE;
sfr I2TOC       = 0xBF;

sfr I2CON       = 0xC0;
sfr I2ADDR      = 0xC1;
sfr ADCRL       = 0xC2;
sfr ADCRH       = 0xC3;
sfr T3CON       = 0xC4;
sfr PWM4H       = 0xC4; //Page1
sfr RL3         = 0xC5;
sfr TL3					= 0xC5; //rename of RL3
sfr PWM5H       = 0xC5;	//Page1
sfr RH3         = 0xC6;
sfr TH3         = 0xC6; //rename of RH3
sfr PIOCON1     = 0xC6; //Page1
sfr TA          = 0xC7;

sfr T2CON       = 0xC8;
sfr T2MOD       = 0xC9;
sfr RCMP2L      = 0xCA;
sfr RCMP2H      = 0xCB;
sfr TL2         = 0xCC; 
sfr PWM4L       = 0xCC; //Page1
sfr TH2         = 0xCD;
sfr PWM5L       = 0xCD; //Page1
sfr ADCMPL      = 0xCE;
sfr ADCMPH      = 0xCF;

sfr PSW         = 0xD0;
sfr PWMPH       = 0xD1;
sfr PWM0H		= 0xD2;
sfr PWM1H		= 0xD3;
sfr PWM2H		= 0xD4;
sfr PWM3H		= 0xD5;
sfr PNP			= 0xD6;
sfr FBD			= 0xD7;

sfr PWMCON0		= 0xD8;
sfr PWMPL       = 0xD9;
sfr PWM0L		= 0xDA;
sfr PWM1L		= 0xDB;
sfr PWM2L		= 0xDC;
sfr PWM3L		= 0xDD;
sfr PIOCON0		= 0xDE;
sfr PWMCON1     = 0xDF;

sfr ACC         = 0xE0;
sfr ADCCON1     = 0xE1;
sfr ADCCON2     = 0xE2;
sfr ADCDLY      = 0xE3;
sfr C0L         = 0xE4;
sfr C0H         = 0xE5;
sfr C1L         = 0xE6;
sfr C1H         = 0xE7;

sfr ADCCON0     = 0xE8;
sfr PICON       = 0xE9;
sfr PINEN       = 0xEA;
sfr PIPEN       = 0xEB;
sfr PIF         = 0xEC;
sfr C2L         = 0xED;
sfr C2H         = 0xEE;
sfr EIP         = 0xEF;

sfr B           = 0xF0;
sfr CAPCON3		= 0xF1;
sfr CAPCON4		= 0xF2;
sfr SPCR        = 0xF3;
sfr SPCR2		= 0xF3; //Page1
sfr SPSR        = 0xF4;
sfr SPDR        = 0xF5;
sfr AINDIDS		= 0xF6;
sfr EIPH        = 0xF7;

sfr SCON_1      = 0xF8;
sfr PDTEN       = 0xF9; //TA Protection
sfr PDTCNT      = 0xFA; //TA Protection
sfr PMEN        = 0xFB;
sfr PMD         = 0xFC;
sfr EIP1        = 0xFE;
sfr EIPH1       = 0xFF;

/*  BIT Registers  */
/*  SCON_1  */
sbit SM0_1      = SCON_1^7;
sbit FE_1       = SCON_1^7; 
sbit SM1_1      = SCON_1^6; 
sbit SM2_1      = SCON_1^5; 
sbit REN_1      = SCON_1^4; 
sbit TB8_1      = SCON_1^3; 
sbit RB8_1      = SCON_1^2; 
sbit TI_1       = SCON_1^1; 
sbit RI_1       = SCON_1^0; 

/*  ADCCON0  */
sbit ADCF       = ADCCON0^7;
sbit ADCS       = ADCCON0^6;
sbit ETGSEL1    = ADCCON0^5;
sbit ETGSEL0    = ADCCON0^4;
sbit ADCHS3     = ADCCON0^3;
sbit ADCHS2     = ADCCON0^2;
sbit ADCHS1     = ADCCON0^1;
sbit ADCHS0     = ADCCON0^0;

/*  PWMCON0  */
sbit PWMRUN     = PWMCON0^7;
sbit LOAD       = PWMCON0^6;
sbit PWMF       = PWMCON0^5;
sbit CLRPWM     = PWMCON0^4;


/*  PSW */
sbit CY         = PSW^7;
sbit AC         = PSW^6;
sbit F0         = PSW^5;
sbit RS1        = PSW^4;
sbit RS0        = PSW^3;
sbit OV         = PSW^2;
sbit P          = PSW^0;

/*  T2CON  */
sbit TF2        = T2CON^7;
sbit TR2        = T2CON^2;
sbit CM_RL2     = T2CON^0;
 
/*  I2CON  */
sbit I2CEN      = I2CON^6;
sbit STA        = I2CON^5;
sbit STO        = I2CON^4;
sbit SI         = I2CON^3;
sbit AA         = I2CON^2;
sbit I2CPX	= I2CON^0;

/*  IP  */  
sbit PADC       = IP^6;
sbit PBOD       = IP^5;
sbit PS         = IP^4;
sbit PT1        = IP^3;
sbit PX1        = IP^2;
sbit PT0        = IP^1;
sbit PX0        = IP^0;

/*  P3  */  
sbit P30        = P3^0;

/*  IE  */
sbit EA         = IE^7;
sbit EADC       = IE^6;
sbit EBOD       = IE^5;
sbit ES         = IE^4;
sbit ET1        = IE^3;
sbit EX1        = IE^2;
sbit ET0        = IE^1;
sbit EX0        = IE^0;

/*  P2  */ 
sbit P20        = P2^0;

/*  SCON  */
sbit SM0        = SCON^7;
sbit FE         = SCON^7; 
sbit SM1        = SCON^6; 
sbit SM2        = SCON^5; 
sbit REN        = SCON^4; 
sbit TB8        = SCON^3; 
sbit RB8        = SCON^2; 
sbit TI         = SCON^1; 
sbit RI         = SCON^0; 

/*  P1  */     
sbit P17	= P1^7;
sbit AIN0	= P1^7;
                 
sbit P10        = P1^0;
sbit PWM0       = P1^0;
sbit P11        = P1^1;
sbit PWM1       = P1^1;
sbit P12        = P1^2;

/*  TCON  */
sbit TF1        = TCON^7;
sbit TR1        = TCON^6;
sbit TF0        = TCON^5;
sbit TR0        = TCON^4;
sbit IE1        = TCON^3;
sbit IT1        = TCON^2;
sbit IE0        = TCON^1;
sbit IT0        = TCON^0;

/*  P0  */  
sbit P00        = P0^0;
sbit INT0       = P0^0;
sbit VREF       = P0^0;

sbit P01        = P0^1;
sbit INT1       = P0^1;
sbit AIN1       = P0^1;

sbit P02        = P0^2;
sbit PWM2       = P0^2;
sbit AIN2       = P0^2;

sbit P03        = P0^3;
sbit PWM3       = P0^3;
sbit TXD        = P0^3;
sbit AIN3       = P0^3;

sbit P04        = P0^4;
sbit SS         = P0^4;
sbit AIN4       = P0^4;

sbit P05        = P0^5;
sbit PWM4       = P0^5;
sbit SPICK      = P0^5;
sbit AIN5       = P0^5;

sbit P06        = P0^6;
sbit SCL        = P0^6;
sbit AIN6       = P0^6;
sbit PWM5       = P0^6;

sbit P07        = P0^7;
sbit AIN7       = P0^7;
sbit PWM6       = P0^7;


//------------------- Define Port as Quasi mode  -------------------
#define P00_Quasi_Mode()				P0M1&=~BIT0;P0M2&=~BIT0
#define P01_Quasi_Mode()				P0M1&=~BIT1;P0M2&=~BIT1
#define P02_Quasi_Mode()				P0M1&=~BIT2;P0M2&=~BIT2
#define P03_Quasi_Mode()				P0M1&=~BIT3;P0M2&=~BIT3
#define P04_Quasi_Mode()				P0M1&=~BIT4;P0M2&=~BIT4
#define P05_Quasi_Mode()				P0M1&=~BIT5;P0M2&=~BIT5
#define P06_Quasi_Mode()				P0M1&=~BIT6;P0M2&=~BIT6
#define P07_Quasi_Mode()				P0M1&=~BIT7;P0M2&=~BIT7
#define P10_Quasi_Mode()				P1M1&=~BIT0;P1M2&=~BIT0
#define P11_Quasi_Mode()				P1M1&=~BIT1;P1M2&=~BIT1
#define P12_Quasi_Mode()				P1M1&=~BIT2;P1M2&=~BIT2
#define P13_Quasi_Mode()				P1M1&=~BIT3;P1M2&=~BIT3
#define P14_Quasi_Mode()				P1M1&=~BIT4;P1M2&=~BIT4
#define P15_Quasi_Mode()				P1M1&=~BIT5;P1M2&=~BIT5
#define P16_Quasi_Mode()				P1M1&=~BIT6;P1M2&=~BIT6
#define P17_Quasi_Mode()				P1M1&=~BIT7;P1M2&=~BIT7
#define P20_Quasi_Mode()				P2M1&=~BIT0;P2M2&=~BIT0
#define P30_Quasi_Mode()				P3M1&=~BIT0;P3M2&=~BIT0


//------------------- Define Port as Push Pull mode -------------------
#define P00_PushPull_Mode()			P0M1&=~BIT0;P0M2|=BIT0
#define P01_PushPull_Mode()			P0M1&=~BIT1;P0M2|=BIT1
#define P02_PushPull_Mode()			P0M1&=~BIT2;P0M2|=BIT2
#define P03_PushPull_Mode()			P0M1&=~BIT3;P0M2|=BIT3
#define P04_PushPull_Mode()			P0M1&=~BIT4;P0M2|=BIT4
#define P05_PushPull_Mode()			P0M1&=~BIT5;P0M2|=BIT5
#define P06_PushPull_Mode()			P0M1&=~BIT6;P0M2|=BIT6
#define P07_PushPull_Mode()			P0M1&=~BIT7;P0M2|=BIT7
#define P10_PushPull_Mode()			P1M1&=~BIT0;P1M2|=BIT0
#define P11_PushPull_Mode()			P1M1&=~BIT1;P1M2|=BIT1
#define P12_PushPull_Mode()			P1M1&=~BIT2;P1M2|=BIT2
#define P13_PushPull_Mode()			P1M1&=~BIT3;P1M2|=BIT3
#define P14_PushPull_Mode()			P1M1&=~BIT4;P1M2|=BIT4
#define P15_PushPull_Mode()			P1M1&=~BIT5;P1M2|=BIT5
#define P16_PushPull_Mode()			P1M1&=~BIT6;P1M2|=BIT6
#define P17_PushPull_Mode()			P1M1&=~BIT7;P1M2|=BIT7
#define P20_PushPull_Mode()			P2M1&=~BIT0;P2M2|=BIT0
#define P30_PushPull_Mode()			P3M1&=~BIT0;P3M2|=BIT0



//------------------- Define Port as Input Only mode -------------------
#define P00_Input_Mode()				P0M1|=BIT0;P0M2&=~BIT0
#define P01_Input_Mode()				P0M1|=BIT1;P0M2&=~BIT1
#define P02_Input_Mode()				P0M1|=BIT2;P0M2&=~BIT2
#define P03_Input_Mode()				P0M1|=BIT3;P0M2&=~BIT3
#define P04_Input_Mode()				P0M1|=BIT4;P0M2&=~BIT4
#define P05_Input_Mode()				P0M1|=BIT5;P0M2&=~BIT5
#define P06_Input_Mode()				P0M1|=BIT6;P0M2&=~BIT6
#define P07_Input_Mode()				P0M1|=BIT7;P0M2&=~BIT7
#define P10_Input_Mode()				P1M1|=BIT0;P1M2&=~BIT0
#define P11_Input_Mode()				P1M1|=BIT1;P1M2&=~BIT1
#define P12_Input_Mode()				P1M1|=BIT2;P1M2&=~BIT2
#define P13_Input_Mode()				P1M1|=BIT3;P1M2&=~BIT3
#define P14_Input_Mode()				P1M1|=BIT4;P1M2&=~BIT4
#define P15_Input_Mode()				P1M1|=BIT5;P1M2&=~BIT5
#define P16_Input_Mode()				P1M1|=BIT6;P1M2&=~BIT6
#define P17_Input_Mode()				P1M1|=BIT7;P1M2&=~BIT7
#define P20_Input_Mode()				P2M1|=BIT0;P2M2&=~BIT0
#define P30_Input_Mode()				P3M1|=BIT0;P3M2&=~BIT0




//-------------------Define Port as Open Drain mode -------------------
#define P00_OpenDrain_Mode()		P0M1|=BIT0;P0M2|=BIT0
#define P01_OpenDrain_Mode()		P0M1|=BIT1;P0M2|=BIT1
#define P02_OpenDrain_Mode()		P0M1|=BIT2;P0M2|=BIT2
#define P03_OpenDrain_Mode()		P0M1|=BIT3;P0M2|=BIT3
#define P04_OpenDrain_Mode()		P0M1|=BIT4;P0M2|=BIT4
#define P05_OpenDrain_Mode()		P0M1|=BIT5;P0M2|=BIT5
#define P06_OpenDrain_Mode()		P0M1|=BIT6;P0M2|=BIT6
#define P07_OpenDrain_Mode()		P0M1|=BIT7;P0M2|=BIT7
#define P10_OpenDrain_Mode()		P1M1|=BIT0;P1M2|=BIT0
#define P11_OpenDrain_Mode()		P1M1|=BIT1;P1M2|=BIT1
#define P12_OpenDrain_Mode()		P1M1|=BIT2;P1M2|=BIT2
#define P13_OpenDrain_Mode()		P1M1|=BIT3;P1M2|=BIT3
#define P14_OpenDrain_Mode()		P1M1|=BIT4;P1M2|=BIT4
#define P15_OpenDrain_Mode()		P1M1|=BIT5;P1M2|=BIT5
#define P16_OpenDrain_Mode()		P1M1|=BIT6;P1M2|=BIT6
#define P17_OpenDrain_Mode()		P1M1|=BIT7;P1M2|=BIT7
#define P20_OpenDrain_Mode()		P2M1|=BIT0;P2M2|=BIT0
#define P30_OpenDrain_Mode()		P3M1|=BIT0;P3M2|=BIT0

sbit		P13			=	P1^3;
sbit		P14			= P1^4;
sbit		P15			= P1^5;
sbit		P16			= P1^6;


#define P00_SET()								P00 = 1
#define P00_CLR()								P00 = 0
#define P00_TOGGLE()						P00 = ~P00

#define P01_SET()								P01 = 1
#define P01_CLR()								P01 = 0
#define P01_TOGGLE()						P01 = ~P01

#define P02_SET()								P02 = 1
#define P02_CLR()								P02 = 0
#define P02_TOGGLE()						P02 = ~P02

#define P03_SET()								P03 = 1
#define P03_CLR()								P03 = 0
#define P03_TOGGLE()						P03 = ~P03

#define P04_SET()								P04 = 1
#define P04_CLR()								P04 = 0
#define P04_TOGGLE()						P04 = ~P04

#define P05_SET()								P05 = 1
#define P05_CLR()								P05 = 0
#define P05_TOGGLE()						P05 = ~P05

#define P06_SET()								P06 = 1
#define P06_CLR()								P06 = 0
#define P06_TOGGLE()						P06 = ~P06

#define P07_SET()								P07 = 1
#define P07_CLR()								P07 = 0
#define P07_TOGGLE()						P07 = ~P07

#define P10_SET()								P10 = 1
#define P10_CLR()								P10 = 0
#define P10_TOGGLE()						P10 = ~P10

#define P11_SET()								P11 = 1
#define P11_CLR()								P11 = 0
#define P11_TOGGLE()						P11 = ~P11

#define P12_SET()								P12 = 1
#define P12_CLR()								P12 = 0
#define P12_TOGGLE()						P12 = ~P12

#define P13_SET()								P13 = 1
#define P13_CLR()								P13 = 0
#define P13_TOGGLE()						P13 = ~P13

#define P14_SET()								P14 = 1
#define P14_CLR()								P14 = 0
#define P14_TOGGLE()						P14 = ~P14

#define P15_SET()								P15 = 1
#define P15_CLR()								P15 = 0
#define P15_TOGGLE()						P15 = ~P15

#define P16_SET()								P16 = 1
#define P16_CLR()								P16 = 0
#define P16_TOGGLE()						P16 = ~P16

#define P17_SET()								P17 = 1
#define P17_CLR()								P17 = 0
#define P17_TOGGLE()						P17 = ~P17

#define P20_SET()								P20 = 1
#define P20_CLR()								P20 = 0
#define P20_TOGGLE()						P20 = ~P20

#define P30_SET()								P30 = 1
#define P30_CLR()								P30 = 0
#define P30_TOGGLE()						P30 = ~P30

#define INTERRUPT_GET()																		EA
#define INTERRUPT_ENABLE()																EA = 1
#define INTERRUPT_DISABLE()																EA = 0
#define INTERRUPT_SAVE()																	{bit _interrupt_temp = EA;
#define INTERRUPT_RESTORE()																EA = _interrupt_temp;}



#define TIMER0_GATE_DISABLE()															TMOD &= ~0x08
#define TIMER0_GATE_ENABLE()															TMOD |= 0x08
#define TIMER0_SET_USE_INTERNAL_SIGNAL()									TMOD &= ~0x04
#define TIMER0_SET_USE_EXTERNAL_SIGNAL()									TMOD |= 0x04
#define TIMER0_SET_13BIT_MANUAL_RELOAD_MODE()							TMOD = (TMOD & ~0x03) | 0x00
#define TIMER0_SET_16BIT_MANUAL_RELOAD_MODE()							TMOD = (TMOD & ~0x03) | 0x01
#define TIMER0_SET_8BIT_AUTO_RELOAD_MODE()								TMOD = (TMOD & ~0x03) | 0x02
#define TIMER0_SET_DOUBLE_8BIT_MANUAL_RELOAD_MODE()				TMOD = (TMOD & ~0x03) | 0x03
#define TIMER0_INTERRUPT_ENABLE()													ET0 = 1
#define TIMER0_INTERRUPT_DISABLE()												ET0 = 0
#define TIMER0_TRIGGER_ENABLE()														TR0 = 1
#define TIMER0_TRIGGER_DISABLE()													TR0 = 0
#define TIMER0_SET_USE_INTERNAL_SIGNAL()									TMOD &= ~0x04
#define TIMER0_SET_USE_EXTERNAL_SIGNAL()									TMOD |= 0x04
#define TIMER0_1T_ENABLE()																CKCON |= 0x08
#define TIMER0_1T_DISABLE()																CKCON &= ~0x08

#define TIMER1_GATE_DISABLE()															TMOD &= ~0x80
#define TIMER1_GATE_ENABLE()															TMOD |= 0x80
#define TIMER1_SET_USE_INTERNAL_SIGNAL()									TMOD &= ~0x40
#define TIMER1_SET_USE_EXTERNAL_SIGNAL()									TMOD |= 0x40
#define TIMER1_SET_13BIT_MANUAL_RELOAD_MODE()							TMOD = (TMOD & ~0x30) | 0x00
#define TIMER1_SET_16BIT_MANUAL_RELOAD_MODE()							TMOD = (TMOD & ~0x30) | 0x10
#define TIMER1_SET_8BIT_AUTO_RELOAD_MODE()								TMOD = (TMOD & ~0x30) | 0x20
#define TIMER1_SET_STOP_MODE()														TMOD = (TMOD & ~0x30) | 0x30
#define TIMER1_INTERRUPT_FLAG_SET()												TF1 = 1
#define TIMER1_INTERRUPT_FLAG_CLEAR()											TF1 = 0
#define TIMER1_INTERRUPT_ENABLE()													ET1 = 1
#define TIMER1_INTERRUPT_DISABLE()												ET1 = 0
#define TIMER1_TRIGGER_ENABLE()														TR1 = 1
#define TIMER1_TRIGGER_DISABLE()													TR1 = 0
#define TIMER1_SET_USE_INTERNAL_SIGNAL()									TMOD &= ~0x40
#define TIMER1_SET_USE_EXTERNAL_SIGNAL()									TMOD |= 0x40
#define TIMER1_1T_ENABLE()																CKCON |= 0x10
#define TIMER1_1T_DISABLE()																CKCON &= ~0x10

#define TIMER2_SET_COMPARE_MODE()													T2CON |= 0x01
#define TIMER2_SET_RELOAD_MODE()													T2CON &= ~0x01
#define TIMER2_SET_PRESCALER(n)														T2MOD = (T2MOD & ~0x70)|((n)<<4)
#define TIMER2_CAPTURE_AUTO_CLEAR_ENABLE()								T2MOD |= 0x08
#define TIMER2_CAPUTRE_AUTO_CLEAR_DISABLE()								T2MOD &= ~0x08
#define TIMER2_COMPARE_AUTO_CLEAR_ENABLE()								T2MOD |= 0x04
#define TIMER2_COMPARE_AUTO_CLEAR_DISABLE()								T2MOD &= ~0x04
#define TIMER2_RELOAD_TRIGGER_SOURCE(n)										T2MOD = (T2MOD & ~0x03)|(n)
#define TIMER2_RELOAD_ENABLE()														T2MOD |= 0x80
#define TIMER2_RELOAD_DISABLE()														T2MOD &= ~0x80
#define TIMER2_SET_RELOAD_VALUE(x)												RCMP2H = (x)>>8;RCMP2L = (x)&0xff
#define TIMER2_CAPTURE_CHANNEL0_ENABLE()									CAPCON0 |= 0x10
#define TIMER2_CAPTURE_CHANNEL0_DISABLE()									CAPCON0 &= ~0x10
#define TIMER2_CAPTURE_CHANNEL1_ENABLE()									CAPCON0 |= 0x20
#define TIMER2_CAPTURE_CHANNEL1_DISABLE()									CAPCON0 &= ~0x20
#define TIMER2_CAPTURE_CHANNEL2_ENABLE()									CAPCON0 |= 0x40
#define TIMER2_CAPTURE_CHANNEL2_DISABLE()									CAPCON0 &= ~0x40
#define TIMER2_CAPTURE_CHANNEL0_FLAG_SET()								CAPCON0 |= 0x01
#define TIMER2_CAPTURE_CHANNEL0_FLAG_CLEAR()							CAPCON0 &= ~0x01
#define TIMER2_CAPTURE_CHANNEL1_FLAG_SET()								CAPCON0 |= 0x02
#define TIMER2_CAPTURE_CHANNEL1_FLAG_CLEAR()							CAPCON0 &= ~0x02
#define TIMER2_CAPTURE_CHANNEL2_FLAG_SET()								CAPCON0 |= 0x04
#define TIMER2_CAPTURE_CHANNEL2_FLAG_CLEAR()							CAPCON0 &= ~0x04
#define TIMER2_CAPTURE_CHANNEL0_EDGE_SELECT(n)						CAPCON1 = (CAPCON1 & ~0x03) | ((n)<<0)
#define TIMER2_CAPTURE_CHANNEL1_EDGE_SELECT(n)						CAPCON1 = (CAPCON1 & ~0x0c) | ((n)<<2)
#define TIMER2_CAPTURE_CHANNEL2_EDGE_SELECT(n)						CAPCON1 = (CAPCON1 & ~0x30) | ((n)<<4)
#define TIMER2_CAPTURE_CHANNEL0_FILTER_ENABLE()						CAPCON2 &= ~0x10
#define TIMER2_CAPTURE_CHANNEL0_FILTER_DISABLE()					CAPCON2 |= 0x10
#define TIMER2_CAPTURE_CHANNEL1_FILTER_ENABLE()						CAPCON2 &= ~0x20
#define TIMER2_CAPTURE_CHANNEL1_FILTER_DISABLE()					CAPCON2 |= 0x20
#define TIMER2_CAPTURE_CHANNEL2_FILTER_ENABLE()						CAPCON2 &= ~0x40
#define TIMER2_CAPTURE_CHANNEL2_FILTER_DISABLE()					CAPCON2 |= 0x40
#define TIMER2_CAPTURE_CHANNEL0_SOURCE_SELECT(n)					CAPCON3 = (CAPCON3 & ~0x0f) | ((n)<<0)
#define TIMER2_CAPTURE_CHANNEL1_SOURCE_SELECT(n)					CAPCON3 = (CAPCON3 & ~0xf0) | ((n)<<4)
#define TIMER2_CAPTURE_CHANNEL2_SOURCE_SELECT(n)					CAPCON4 = (CAPCON4 & ~0x0f) | ((n)<<0)
#define TIMER2_INTERRUPT_FLAG_SET()												TF2 = 1
#define TIMER2_INTERRUPT_FLAG_CLEAR()											TF2 = 0
#define TIMER2_INTERRUPT_ENABLE()													EIE |= 0x80
#define TIMER2_INTERRUPT_DISABLE()												EIE &= ~0x80
#define TIMER2_TRIGGER_ENABLE()														TR2 = 1
#define TIMER2_TRIGGER_DISABLE()													TR2 = 0
#define TIMER2_1T_ENABLE()																//not support
#define TIMER2_1T_DISABLE()																//not support


#define TIMER3_SET_PRESCALER(n)														T3CON = (T3CON & ~0x07)|(n)
#define TIMER3_INTERRUPT_FLAG_SET()												T3CON |= 0x10
#define TIMER3_INTERRUPT_FLAG_CLEAR()											T3CON &= ~0x10
#define TIMER3_INTERRUPT_ENABLE()													EIE1 |= 0x02
#define TIMER3_INTERRUPT_DISABLE()												EIE1 &= ~0x02
#define TIMER3_TRIGGER_ENABLE()														T3CON |= 0x08
#define TIMER3_TRIGGER_DISABLE()													T3CON &= ~0x08
#define TIMER3_1T_ENABLE()																//not support
#define TIMER3_1T_DISABLE()																//not support

#define TIMER_LOAD_VALUE16(period,clk,d12)								(65536UL - period*clk/d12)
#define TIMER_LOAD_VALUE8(period,clk,d12)									(256 - period*clk/d12)
#define UART_SET_TIMER_VALUE16(baudrate, clk, d12, m2)		(65536UL - m2*clk/baudrate/32/d12)
#define UART_SET_TIMER_VALUE8(baudrate, clk, d12, m2)			(256 - m2*clk/baudrate/32/d12)



#define UART0_SET_SYNCRONOUS_MODE()												SCON = (SCON & ~0xc0) | (0<<6)
#define UART0_SET_VARIANT_BAUDRATE_8BIT_MODE()						SCON = (SCON & ~0xc0) | (1<<6)
#define UART0_SET_FIXED_BAUDRATE_9BIT_MODE()							SCON = (SCON & ~0xc0) | (2<<6)
#define UART0_SET_VARIANT_BAUDRATE_9BIT_MODE()						SCON = (SCON & ~0xc0) | (3<<6)
#define UART0_RECEIVE_ENABLE()														SCON |= 0x10
#define UART0_RECEIVE_DISABLE()														SCON &= ~0x10
#define UART0_MULTIHOST_ENABLE()													SCON |= 0x20
#define UART0_MULTIHOST_DISABLE()													SCON &= ~0x20
#define UART0_BAUDRATE_DOUBLE_ENABLE()										PCON |= 0x80
#define UART0_BAUDRATE_DOUBLE_DISABLE()										PCON &= ~0x80
#define UART0_FRAME_ERROR_DETECTION_ENABLE()							PCON |= 0x40
#define UART0_FRAME_ERROR_DETECTION_DISABLE()							PCON &= ~0x40
#define UART0_SYNCRONOUS_MODE_BAUDRATE_SPEEDUP_ENABLE()		SCON |= 0x20
#define UART0_SYNCRONOUS_MODE_BAUDRATE_SPEEDUP_DISABLE()	SCON &= ~0x20
#define UART0_BAUDRATE_GENERATOR_SELECT(n)								T3CON = (T3CON & ~0x20) | ((n)<<5)	//0:select timer1, 1:select timer3
#define UART0_GET_SBUF()																	SBUF
#define UART0_SET_SBUF(v)																	SBUF = (v)
#define UART0_TX_INTERRUPT_FLAG_GET()											TI
#define UART0_TX_INTERRUPT_FLAG_SET()											TI = 1
#define UART0_TX_INTERRUPT_FLAG_CLEAR()										TI = 0
#define UART0_RX_INTERRUPT_FLAG_GET()											RI
#define UART0_RX_INTERRUPT_FLAG_SET()											RI = 1
#define UART0_RX_INTERRUPT_FLAG_CLEAR()										RI = 0
#define UART0_INTERRUPT_ENABLE()													ES = 1
#define UART0_INTERRUPT_DISABLE()													ES = 0
#define UART0_INTERRUPT_PRIORITY_GET()										(((IPH&0x10)>>3)|((IP&0x10)>>4))
#define UART0_INTERRUPT_PRIORITY_SET(n)										IPH = (IPH&~0x10)|((n&~0x02)<<3);IP = (IP&~0x10)|((n&~0x01)<<4)

#define UART1_SET_SYNCRONOUS_MODE()												SCON_1 = (SCON_1 & ~0xc0) | (0<<6)
#define UART1_SET_VARIANT_BAUDRATE_8BIT_MODE()						SCON_1 = (SCON_1 & ~0xc0) | (1<<6)
#define UART1_SET_FIXED_BAUDRATE_9BIT_MODE()							SCON_1 = (SCON_1 & ~0xc0) | (2<<6)
#define UART1_SET_VARIANT_BAUDRATE_9BIT_MODE()						SCON_1 = (SCON_1 & ~0xc0) | (3<<6)
#define UART1_RECEIVE_ENABLE()														SCON_1 |= 0x10
#define UART1_RECEIVE_DISABLE()														SCON_1 &= ~0x10
#define UART1_MULTIHOST_ENABLE()													SCON_1 |= 0x20
#define UART1_MULTIHOST_DISABLE()													SCON_1 &= ~0x20
#define UART1_BAUDRATE_DOUBLE_ENABLE()										T3CON |= 0x80
#define UART1_BAUDRATE_DOUBLE_DISABLE()										T3CON &= ~0x80
#define UART1_FRAME_ERROR_DETECTION_ENABLE()							T3CON |= 0x40
#define UART1_FRAME_ERROR_DETECTION_DISABLE()							T3CON &= ~0x40
#define UART1_BAUDRATE_GENERATOR_SELECT(n)								//NO NEED.CAN ONLY USE TIMER3 AS BAUDRATE GENERATOR
#define UART1_GET_SBUF()																	SBUF_1
#define UART1_SET_SBUF(v)																	SBUF_1 = (v)
#define UART1_TX_INTERRUPT_FLAG_GET()											(SCON_1&0x02)>>1
#define UART1_TX_INTERRUPT_FLAG_SET()											SCON_1 |= 0x02
#define UART1_TX_INTERRUPT_FLAG_CLEAR()										SCON_1 &= ~0x02
#define UART1_RX_INTERRUPT_FLAG_GET()											(SCON_1&0x01)
#define UART1_RX_INTERRUPT_FLAG_SET()											SCON_1 |= 0x01
#define UART1_RX_INTERRUPT_FLAG_CLEAR()										SCON_1 &= ~0x01
#define UART1_INTERRUPT_ENABLE()													EIE1 |= 0x01
#define UART1_INTERRUPT_DISABLE()													EIE1 &= ~0x01
#define UART1_INTERRUPT_PRIORITY_GET()										(((EIPH1&0x01)<<1)|(EIP1&0x01)
#define UART1_INTERRUPT_PRIORITY_SET(n)										EIPH1 = (EIPH1&~0x01)|((n&~0x02)>>1);EIP1 = (EIP1&~0x01)|(n&~0x01)


#define ADC_ENABLE(ch)																		ADCCON0&=0xF0;ADCCON0|=(ch);ADCCON1|=1
#define ADC_DISABLE()																			ADCCON1&=~1
#define ADC_CHANNEL_DIGITAL_INPUT_DISABLE(ch)							AINDIDS&=~(1<<(ch))
#define ADC_CHANNEL_DIGITAL_INPUT_ENABLE(ch)							AINDIDS|=(1<<(ch))
#define ADC_RESULT()																			(ADCRH<<4)|(ADCRL&0x0F)
#define ADC_START()																				ADCS = 1
#define ADC_STOP()																				ADCS = 0
#define ADC_INTERRUPT_FLAG_GET()													ADCF
#define ADC_INTERRUPT_FLAG_SET()													ADCF = 1
#define ADC_INTERRUPT_FALG_CLEAR()												ADCF = 0
#define ADC_INTERRUPT_ENABLE()														EADC = 1
#define ADC_INTERRUPT_DISABLE()														EADC = 0
#define ADC_INTERRUPT_PRIORITY_GET()											(((IPH&0x40)>>5)|((IP&0x40)>>6))
#define ADC_INTERRUPT_PRIORITY_SET(n)											IPH = (IPH&~0x40)|((n&~0x02)<<5);IP = (IP&~0x40)|((n&~0x01)<<6)


#define INTERRUPT_VECTOR_EX0							0
#define INTERRUPT_VECTOR_TIMER0						1
#define INTERRUPT_VECTOR_EX1							2
#define INTERRUPT_VECTOR_TIMER1						3
#define INTERRUPT_VECTOR_UART0						4
#define INTERRUPT_VECTOR_TIMER2						5
#define INTERRUPT_VECTOR_I2C							6
#define INTERRUPT_VECTOR_GPIO							7
#define INTERRUPT_VECTOR_LVD							8
#define INTERRUPT_VECTOR_SPI							9
#define INTERRUPT_VECTOR_WDT							10
#define INTERRUPT_VECTOR_ADC							11
#define INTERRUPT_VECTOR_TIMER2_CAPTURE		12
#define INTERRUPT_VECTOR_PWM							13
#define INTERRUPT_VECTOR_PWM_BREAK				14
#define INTERRUPT_VECTOR_UART1						15
#define INTERRUPT_VECTOR_TIMER3						16
#define INTERRUPT_VECTOR_WKT							17

sfr RCTRIM0     = 0x84;
sfr RCTRIM1     = 0x85;

#define MODIFY_HIRC_166()																															\
{																																											\
	unsigned char hircmap0,hircmap1;																										\
	unsigned int trimvalue16bit;																												\
																																											\
	if((PCON&0x10)==0x10)																																\
	{																																										\
		trimvalue16bit = ((((unsigned int)RCTRIM0)<<1) | RCTRIM1&0x01) - 15;							\
		hircmap1 = trimvalue16bit&0x01;																										\
		hircmap0 = trimvalue16bit>>1;																											\
		TA = 0xAA;TA = 0x55;RCTRIM0 = hircmap0;																						\
		TA = 0xAA;TA = 0x55;RCTRIM1 = hircmap1;																						\
		PCON &= ~0x10;																																		\
	}																																										\
}
	

#endif
